Technical Field
Embodiments of the present disclosure relate to techniques for reducing the influence of cycle slippage in a clock recovery circuit.
Description of the Related Art
FIG. 1 shows a generic transmission system in which a transmitter 1 transmits data over a communication channel 2 to a receiver 3. For example, the communication channel may be a cable, an optical fiber or a radio communication channel.
For this purpose, the transmitter 1 may comprise a transmitter circuit 10, such as a network processor, generating data D_TX and an interface circuit 12 configured to receive the data D_TX and transmit a corresponding signal to the communication channel 2. For example, the interface circuit 12 may convert the data D_TX into an optical signal, e.g., for transmission over an optical fiber.
Specifically, in the example considered, the transmitter circuit 10 is synchronous, e.g., generation of the data signal D_TX is synchronized with a transmission clock signal CLK_TX, generated e.g., by a clock generator 14, such as a voltage controlled oscillator and possibly a PLL (Phase-Locked Loop).
Similarly, the receiver 3 may comprise an interface circuit 32 configured to receive the signal transmitted over the communication channel 2 and provide a respective data signal D_RX to a receiver circuit 30, such as a network processor, configured to process the received data D_RX. For example, the interface circuit 32 may convert an optical signal received from an optical fiber again into an electric signal. For this purpose, the interface circuit 32 may comprise, e.g., a photo-diode, a trans-impedance amplifier (TIA) and a low-noise amplifier (LNA).
In the example considered, also the receiver circuit 30 is synchronous, i.e., processing of the data signal D_RX is synchronized with a clock signal.
For example, in FIG. 1, the operation of the receiver circuit 30 is synchronized with a reception clock signal CLK_RX generated by a clock generator 34, such as a voltage controlled oscillator and possibly a PLL.
Accordingly, in order to correctly receive the data D_RX, the clock signal CLK_RX should correspond to the clock signal CLK_TX used for transmission (neglecting the possibility of performing an oversampling of the data). Moreover, especially in case of high data rates, which renders oversampling complicated, the data D_RX should be phase aligned with respect to the reception clock signal CLK_RX. Accordingly, the receiver 3 may also comprise a phase shifter 36, such as a Delay Locked Loop (DLL), interposed between the interface 32 and the receiver circuit 30. Specifically, this phase shifter 36 may be configured to generate a delayed signal D_RX′ being synchronized with the clock signal CLK_RX.
Often the receiver circuit 30 has to be able to operate with different transmission rates, e.g., because the transmitter circuit 10 may support different transmission rates. Moreover, also the clock signals CLK_TX and CLK_RX may not correspond exactly.
FIG. 2 shows in this respect an embodiment, in which a clock and data recovery (CDR) circuit 50 is used to autonomously estimate the clock signal CLK_TX′ used for transmission of the data D_TX.
Specifically, the CDR 50 permits to extract the transmitted data sequence D_RX′ from the distorted received signal D_RX and to recover the associated clock signal CLK_TX′.
As shown in FIG. 3, the circuit 50 usually comprises a dock recovery circuit 54 configured to detect the transitions in the received data signal D_RX and generate a periodic clock CLK_TX′.
Generally, two types of clock recovery circuits 54 exits: clock recovery circuits 54 operating with a reference clock signal CLK_REF, generated e.g., by the oscillator 34, and clock recovery circuits 54 operating without a reference clock signal CLK_REF.
Often the circuit 50 comprises also a decision circuit 52, such as one or more flip-flops, e.g., D flip-flops, connected in cascade, which sample the received data signal D_RX in accordance with the recovered clock signal CLK_TX′. Accordingly, the sampled data signal D_RX′ at the output of the decision circuit 52 usually has less jitter, skew and/or noise.
For example, the architecture shown in FIG. 2 may be used in a Synchronous Optical Network (SONET), which is often used in the transport infrastructure of wide area networks (WAN) backbones, e.g., the Internet. See, The related standards concerning SONET.
Especially for high data rates, the implementation of the clock recover circuit 54 may impact the reception of the data. For this reason a lot of different implementations of CDR circuits have been proposed in literature.
For example, FIG. 4 shows a PLL based CDR architecture without reference clock.
Specifically, in the example considered, the clock-recover circuit 54 comprises a voltage controlled oscillator (VCO) 540, such as a series of inverters with variable supply voltage, and at least a first control loop.
Specifically, in the example considered, the first control loop represents a phase tracking loop comprising a phase detector (PD) 542, a charge pump 544 and a loop filter (LF) 546.
Specifically, the phase detector 542 performs a phase comparison between the input data D_RX and the voltage-controlled oscillator output CLK_TX′. Accordingly, in the example considered, the phase detector 542 varies (via the charge pump 544 and the loop filter 546) the control voltage of the oscillator 540 in order to perform a tuning of the clock signal CLK_TX′ thereby adjusting the oscillation frequency and the phase shift of the clock signal CLK_TX′ with respect to the data signal D_RX′.
Often, the PLL (comprising the components 540-546) is only used for the fine tuning of the oscillation frequency, and a reference clock signal or a second (optional) control loop is used for the coarse tuning.
For example, in FIG. 4, the second control loop represents a frequency tracking loop comprising a frequency detector (FD) 548, a charge pump 550 and a loop filter, which may also correspond to the loop filter 546. Specifically, the frequency detector 548 performs a frequency comparison between the input data D_RX and the voltage-controlled oscillator output CLK_TX′. Specifically, the control voltage is varied (i.e., increased or decreased) until the oscillation frequency of the signal CLK_TX′ corresponds approximately to the data rate of the input signal D_RX.
Typically, the frequency tracking loop is activated during start-up or loss of synchronization in order to generate the control voltage for the oscillator 540 via the charge pump 550. Once the frequency difference falls within given limits, the phase tracking loop is activated and the phase detector 542 varies the control voltage of the oscillator 540 in order to perform a fine tuning of the clock signal CLK_TX′ thereby adjusting the oscillation frequency and phase of the clock signal CLK_TX′ with respect to the data signal D_RX.
Similar PLL controls (comprising a phase detector, a charge pump and a loop filter) are used in most CDR architectures (with or without reference clock) in order to perform a fine tuning of the oscillation frequency and phase of the clock signal CLK_TX′ generated by a voltage controlled oscillator. Reference can be made for this purpose, e.g., to document Ming-ta Hsieh and Gerald E. Sobelman, “Architectures for Multi-Gigabit Wire-Linked Clock and Data Recovery”, IEEE Circuits and Systems Magazine, December 2008, showing example topologies of CDR circuits.
FIG. 5 shows a possible implementation of the decision circuit 52, which is known. Specifically, in the example of FIG. 5 considered, the decision circuit 52 is based on a DLL which comprises a voltage controlled delay line (VCDL) 522, such as a series of inverters with variable supply voltage, and at least a phase tracked control loop comprising a phase detector 524, a charge pump 526 and a loop filter 528, such as a capacitor.
Specifically, the received data signal D_RX is provided at input to the voltage controlled delay line, which delays the data signal D_RX as a function of a given control voltage. The delayed data signal is then provided to the phase detector 524 which generates via the charge pump 526 and the loop filter 528 the control voltage for the voltage controlled delay line 522, thereby generating the signal D_RX′ which is delayed with respect to the received signal D_RX but synchronized with the clock signal CLK_TX. Generally, also in this case, the delayed data signal may be sampled by one or more flip-flops 530 connected in cascade and which are driven by the clock signal CLK_TX′.
Often the combination of the PLL architecture for the clock recovery (with or without an additional frequency control loop) and the DLL architecture for the data recovery is called “PLUDLL CDR”. For other example decision circuits, see also, e.g., W. Rhee, Soyuer M. “A 1O-Gb/s CMOS clock and data recovery circuit using a secondary DLL”, Proceedings of IEEE Custom Integrated Circuits Conf., September 2003, pp. 81-84.